1. Cross Reference to Related Applications
This application is related to Application, Ser. No. 08/897,165, filed on the filing date of this application, entitled REDUCTION OF DEPLETION SPREADING SIDEWAYS UTILIZING SLOTS, Application, Ser. No. 08/897,265, filed on the filing date of this application, entitled ELIMINATION OF RADIUS OF CURVATURE EFFECTS ON P-N JUNCTION AVALANCE BREAKDOWN USING SLOTS, Application, Ser. No. 08/897,167, filed on the filing date of this application, entitled USE OF MULTIPLE SLOTS SURROUNDING BASE REGION OF A BIPOLAR JUNCTION TRANSISTOR TO INCREASE CUMULATIVE BREAKDOWN VOLTAGE and Application, Ser. No. 08/897,082, filed on the filing date of this application, entitled USE OF SLOTS IN DEEP ISOLATION AND COLLECTOR PICKUP REGIONS FOR MINIMIZATION OF SUB-COLLECTOR UP-DIFFUSION.
2. Field of the Invention
This invention relates generally to high voltage semiconductor devices. More particularly, this invention relates to high voltage bipolar semiconductor devices having tungsten filled slots as ground plane that reduce high frequency signal degradation and parasitic signal propagation.
3. Discussion of the Related Art
The bipolar transistor is an electronic device with two pn-junctions in very close proximity. There are three device regions: an emitter region, a base region, and a collector region. The two pn-junctions are known as the emitter-base (EB) junction and the collector-base (CB) junction. Modulation of the current in one pn-junction by means of a change in the bias of the other nearby pn-junction is called bipolar-transistor action. Because the mobility of minority carriers (electrons) in the base region of npn transistors is higher than that of holes in the base of pnp transistors, higher frequency operation and higher speed performances can be obtained with npn devices. For this reason, the following discussion will be in terms of npn transistors but it is to be understood that the discussion is applicable to pnp transistors as well.
The desired device characteristics of bipolar transistors include: high current gain, high frequency ac operation, fast switching speed, high device-breakdown voltages, minimum device size (to achieve high functional density) and high reliability of device operation. In order for high-frequency ac performance and fast switching speed to be achieved, the parasitic resistances of the transistor; R.sub.E, R.sub.B, and R.sub.C, and the parasitic junction capacitances; C.sub.EB, C.sub.CB, and C.sub.CB must be minimized. In addition, high-level injection effects, for example, the Kirk effect should be avoided. For faithful amplification of ac signals, the Early voltage must be high.
Another factor that must be considered in transistors are the errors due to parasitic signal propagation. As the semiconductor devices are being shrunk to meet the needs of consumers and to satisfy the increasing demand for faster and faster semiconductor devices, the errors due to parasitic signal propagation and high frequency signal degradation are becoming more and more critical.
The ground planes typically used today for applications such as analog circuits are the silicon substrates under the active region on the surface on which the transistors/circuits are located. The ground plane is then contacted with a backside contact.
In complex circuits with many interconnected transistors, a ground plane can eliminate resonances causing signal attenuation or non-linearity that is critical for analog applications, and in more general terms reduce electrical noise. This type of extraneous signal propagation occurs via the substrate.
A second path for extraneous signal propagation occurs between the interconnect lines. The use of a ground plane allows reduction of cross-talk or noise generation on adjacent interconnect lines; the electric field radiating from a signal line terminates on the ground plane rather than coupling to an adjacent line. With a complete ground plane, interconnect lines with controlled impedances can also be achieved. This becomes increasingly important as the frequencies at which signals propagate increase leading to enhanced sensitivity of an interconnect line to its surroundings. While the problems discussed above play a critical role in high frequency analog circuits, they are becoming significant issues for digital applications operating at very high clock frequencies.
U.S. Pat. No. 5,485,029 to Crabbe et al. describes an on-chip ground plane for reducing high frequency signal degradation and parasitic signal propagation. The ground plane in Crabbe et al. is a buried low resistivity semiconductor region in a plurality of non-device regions of the chip with reach-through regions electrically connected to the buried low resistivity semiconductor region. A front-side contact is electrically connected to the reach-through regions for electrically coupling the reach-through regions and the buried low resistivity semiconductor region to a ground potential to electrically ground the on-chip ground plane.
The drawback to the prior art device disclosed in Crabbe et al. is that isolation structures are still needed and the reach-through regions require additional space on the chip.
Therefore, what is needed is a semiconductor device with an on-chip ground plane that does not require additional space on the chip and that is effective in reducing high frequency signal degradation and parasitic signal propagation.